The flexible board architecture supports the larger Xilinx Virtex 6 devices, including the LX240T, LX365T, LX550T, SX315T and SX475T. Initially supporting the SX240T-ES device, other density options will be offered as soon as they are available.
The PCIe to Local Bus bridge design provides a simple, high-performance interface between the host and FPGA system. This bridge, coupled with the firm's software development kit, speeds the development of complex cores while increasing available FPGA resources.
There is 1 or 2Gbyte of DDR3 sdram supporting transfer rates of up to 3.2Gbyte/s and arranged in four independent banks for more flexibility. Battery back-up of IP encryption keys is provided to improve security and design protection.
Up to 146 LV cmos and LVDS IO and eight high-speed serial links are provided to the front connectors, while 12 high-speed serial links, an x4 PCI Express interface and 24 GPIO are provided as standard to the rear connectors.
An additional 32 GPIO can be supported through an optional Pn4 connector. Application specific IO options are also available via a range of front-panel adapters, including LVDS, high-performance analogue, Cameralink and optical and copper Rocket IO.
The software development kit includes reference designs, API and drivers for Windows, Linux and VxWorks.