The history of programmable integrated circuits – in all the various meanings of the term – is at root a story of bringing flexibility to circuit design, while meeting ever-growing demands for complexity. In the early days of logic design there were logic gates in individual packages, and somewhat later, MSI.
The microprocessor opened up one route to providing more complex functionality, delivered by executing sequential software instructions; designers who needed greater logic density while preserving the dedicated resource of hard-wired circuitry turned to asics in the form of gate arrays. Making those structures programmable rather than metal-mask-defined delivered a great step forward in the shape of the first FPGAs.
Now, after many generations of product development, the term FPGA itself is scarcely adequate as a description for some of the most versatile devices on the market today. The same silicon die can host not only a large array of customisable logic, and a fully-featured, powerful microcontroller with all its peripherals, but also a suite of analogue function blocks with performance to match any of the standard parts that an embedded system designer might select for a typical project.
The assembly of all of these elements into a single device; that is a mixed-signal FPGA, is a classic case of the whole being greater than the sum of the parts, to the extent of enabling designers of powerful embedded systems to aspire to a single-chip product.
As is so often the case with silicon device evolution, Moore's Law and progress from one process node to the next are major contributors to the feature set of the latest mixed-signal FPGAs. They are not, however, designed to the same objectives as the latest generations of highest-density, pure-logic FPGAs, presently being announced on 28nm silicon processes and with up to two million logic cells. Those devices belong to a separate strand of FPGA evolution, aiming always for the ultimate logic capacity, with the largest parts costing (as always at the density leading-edge) many hundreds of dollars. Mixed-signal FPGAs are developing in a very different direction.
Optimal process
Development of stable, high-performance analogue functions always lags that of digital in any silicon process. The unique opportunity presented by flash-based FPGA technology, which is usually a node or two behind the most advanced sram based FPGAs, is that it can host high performance analogue blocks, together with programmable logic arrays big enough to contain complete applications, plus a large assemblage of pre-diffused hard logic functions, all in a silicon area. The cost and form function benefits of integration provide a compelling design platform for today's embedded, single chip designs.
What constitutes high performance analogue in this context? You might look for analogue-to-digital converters – pivotal functional blocks for gathering input data for any embedded system – of 10 or 12bit resolution, and several hundred kilo-samples per second conversion rate. Among a range of analogue blocks optimised for the embedded-system environment, you might also expect to see accurate, high-speed comparators that will make decisions on a sub-100ns timescale.
Analogue circuit performance can be delivered hand-in-hand with flash memory, when that is used for the configuration memory of the chips. Programming flash memory cells requires elevated voltages relative to the operating voltage level of the logic itself; having made the investment in a process that supports flash, the device manufacturer has one of the key building blocks to build linear circuits with useful rail-to-rail levels, and excellent dynamic range.
Close coupling of analogue functions with on-chip logic opens up new possibilities; for example, complete sequences of analogue signal processing operations can run under control of an independent state-machine-like module.
As the logic portion of such a device is standard cmos, the IC designer can include blocks of sram in the feature set. In contrast to an FPGA that uses sram for its configuration memory, a flash-based chip requires no external read-only memory, and does not have to load its configuration when it powers-up – it is ready to start operating immediately. And with system performance of over 300MHz, performance of the underlying programmable logic array is unlikely to be a constraint on most embedded-system designs.
Hard, soft or discrete?
The option to include a processor core on an FPGA device has existed over several generations of products from multiple manufacturers. The two main options have been for the FPGA vendor to include a pre-diffused section of the die hosting a core in a standard architecture – one available as intellectual property and used by microcontroller vendors as the basis for stand-alone MCUs – or, a proprietary soft core, loaded into a section of the logic array at boot time along with the rest of the logic configuration. The latter is attractive in that the designer can configure just the MCU function set needed, with exactly the peripherals the application requires and no more.
However, such a core can consume an appreciable portion of the available logic on a standard FPGA and cost significantly more than powerful stand-alone microcontrollers, leaving many designers to continue with the conventional architecture choice of a stand-alone microcontroller sitting alongside their FPGA.
With the latest fully-integrated devices, the necessity to make that choice disappears; the MCU core is fully embedded, takes up a very small area on the die (and thus adds little to the cost) and employs an industry-standard architecture, such as Arm's Cortex-M3 microprocessors, with well-known and well-understood development tool chains. Nor is the perennial issue of selecting the MCU with the best-fit peripheral set a problem. The programmable device vendor will have configured a hard peripheral set that meets the needs of the great majority of projects. However, if its complement of, say, two timers, or two uarts, are not enough it is a straightforward exercise to configure extra functions in the logic array.
Design tool support
As is always the case with complex programmable integrated circuits, a significant part of the offering lies in the area of development tools. Process technology allows the chip maker to build a device in which dense logic arrays sit alongside a powerful microprocessor core and rich analogue resources: it is the development environment which turns that silicon offering into a compelling choice for the system designer.
The challenge is considerable; designers used to working in several different styles, in different hardware environments, will all be implementing their ideas within a single chip. Engineers who normally design with conventional FPGAs are used to a hardware description language (HDL), simulation-based design flow, while analogue circuit designers are experienced in refining their concepts by hardware prototyping. Completing the team are engineers from the microcontroller domain, working primarily with code in C or some other language.
The development tool context for the mixed-signal FPGA has to enable each of these styles to come together effectively, in a way that reflects the close coupling of the hardware resources of the chip. More than that, it has to enable engineers from any of those disciplines to be effective if they extend their reach beyond their own comfort zone. The designer of, for example, a motor-control function will be mainly concerned with writing the C for his control algorithms, and perhaps with implementing the real-time, DSP-like aspects of the task in programmable logic. But the tools should allow him or her to step across the boundaries to configure the amplifiers and A-D converters needed to capture voltage, current or speed signals, or to convert PWM logic signals into power-FET gate drives. Ideally, this becomes a matter of drag-and-drop on-screen configuration, and entering parameter values.
Thinking of the cross-discipline design task in this way highlights some of the beneficial consequences of moving a project into such a highly integrated environment. Clearly, there is simple bill-of-materials saving if a parts list of front-end linear chips, microcontroller and FPGA (with its attendant rom, if not a flash-based chip), plus all their accompanying passive components, is reduced to a single programmable device. As ever, the designer or project manager will have to make those calculations, placing a value on the PCB-area saved, and the increase in reliability that follows from simpler layout and fewer connections.
The task of laying out input-signal conditioning circuitry for stability and low noise performance is not trivial; in the programmable-chip context it becomes a graphical-interface task to specify the interconnections on-chip: likewise, on-chip buses with bandwidths of multiple Gbit/s entirely eliminate the problem of routing dense bus connections between, say, processor and dedicated-logic accelerator blocks.
Other benefits that flow from the single-chip, mixed-signal FPGA approach include design security; many engineers already recognise that the intellectual property in their design is better-protected when they use a flash-based part, as the bit-stream that configures an sram-based device at power-up is not vulnerable to interception. The mixed-signal programmable architecture extends that protection to the IP in virtually all the design.
Christian Plante is director of product marketing at Actel